1. Field of the Invention
The present invention generally relates to digital control of pulse width modulators (PWMs), which, when digitally controlled, are sometimes referred to as digital pulse width modulators (DPWMs) and, more particularly, to pulse width modulation for control of output voltage of switching voltage regulators and power converters.
2. Description of the Prior Art
Pulse width modulation is well-known and has been used in a wide variety of electrical and electronic circuits because a pulse width modulated output (or the positive-going and/or negative-going transitions at the leading and trailing edges of a pulse or the like) can often be used to provide direct control of a circuit and possible simplification of the circuit for that reason. In particular, pulse width modulation for providing voltage regulation in switching power supplies and power converters is a particularly important application since it allows substantial improvement in efficiency over analog, unswitched voltage regulators which require an often substantial voltage drop across the regulator at relatively high current, thus dissipating substantial power. In contrast, in a switching voltage regulator, assuming adequate ripple filtering, the output voltage is controlled as a function of the switching duty cycle (the ratio of on-time of the switching to the switching cycle period); which duty cycle can be adjusted in accordance with a load current drawn to maintain the regulator output voltage within a small voltage tolerance. Essentially, a switching power converter or voltage regulator controls the proportion of time an input voltage is applied and thus input current provided to a filter. The regulated output voltage will therefore be some function of the input voltage and duty cycle of its application when input and output currents are equal.
Analog control circuits for controlling PWM circuits for voltage regulators and switching circuits are well-known. However, the current trend is toward using digital control circuits to obtain numerous advantages such as generally reduced power dissipation and noise immunity even though digital control circuits can only provide discrete nominal values of output voltage while modern digital circuits are being designed to operate at lower voltages and higher currents and with increasingly complex and stringent voltage regulation requirements. Therefore, use of digital control for switching voltage regulators and power converters imposes additional unavoidable design trade-offs in order to control the PWMs thereof with sufficient resolution and the design of digital pulse width modulators (DPWMs), sometimes referred to as a DPWM block, has thus become critical in several respects.
Specifically, there are currently three basic approaches to DPWM design: a counter-based DPWM, a delay line-based DPWM and a hybrid of these two types. In a counter-based DPWM, the input clock is counted by a counter and the counted number is compared with a (generally fed-back) value to control pulse width. This structure requires only a small footprint on a chip but high resolution requires high clock rates which ultimately causes relatively high power consumption. In a delay line-based DPWM, time slots are generated by the propagation delay of a pulse through cells of the delay line which are then selected by a multiplexer to generate PWM control signals. This type of DPWM has comparatively lower power consumption than a counter-based DPWM having comparable resolution but requires substantially more chip space than a counter-based DPWM. Additionally, a delay line-based DPWM is subject to variation of delay resolution due to operating temperature, manufacturing process variation and supply voltage variation.
Due to the complementary characteristics of these two approaches, the hybrid type DPWM has become popular for controlling pulse width modulation; using a counter-based approach for developing coarse time slots (thus allowing a low frequency clock to be used) and a delay line-based approach for fine time slot control (thus allowing use of a shorter delay line corresponding to a single coarse time slot. However, hybrid DPWMs still require substantial area for fine time slot resolution (typically about 100-150 psec.) and a relatively large number of delay cells (typically about 64 to 256) and also suffer from variation of delay resolution due to the causes noted above although such variation will generally be reduced as the maximum delay available from a delay line is reduced.
Further, for currently required and foreseeable resolution requirements for accuracy of voltage regulation, relatively high clock frequencies with associated relatively high power consumption are required even for relatively coarse voltage regulation while variation in delay line properties are becoming less tolerable. Thus requirements for increasingly accurate voltage regulation have heretofore been unavoidably linked to increased power consumption in DPWMs due to the increased clock frequency required to provide increased duty cycle resolution. Moreover, it has been considered desirable to maintain the switching frequency of a switched regulator substantially constant and relatively high to achieve good and consistent speed of response to changes in load (which, for many modern digital circuits such as microprocessors can vary widely and rapidly); requiring correspondingly rapid variation in duty cycle to accommodate such variation in the load and since high switching frequency power converters can provide high power density. Accordingly, the clock frequency must generally be a large (e.g. 50 or more) multiple of the regulator switching frequency to obtain acceptably high duty cycle resolution within each switching cycle.